The present invention relates to a semiconductor device and an adjustment method for the semiconductor device. More particularly, the present invention relates to a semiconductor device used for wireless communication and an adjustment method for such a semiconductor device.
A miniaturized CMOS (Complementary Metal Oxide Semiconductor) process is increasingly used even for an RF (Radio Frequency) IC (Integrated Circuit) such as a wireless communication LSI (Large Scale Integration) circuit. It is demanded that signal processing be performed in the miniaturized CMOS process with higher accuracy than in a related-art semiconductor manufacturing process. However, the miniaturized CMOS process is inferior in analog characteristics to the related-art semiconductor manufacturing process. It is therefore important to use a method of, for example, performing calibration after manufacture to improve the characteristics of a manufactured semiconductor device.
In a currently available RFIC, an interface for communicating with an LSI circuit, which performs baseband processing, is digitized. Therefore, the RFIC has a built-in ADC (Analog-to-Digital Converter) that receives an analog signal from an antenna and converts the analog signal to its digital equivalent. It is necessary that the ADC be also calibrated to meet desired conditions for characteristics.
However, when, for instance, W-CDMA (Wideband Code Division Multiple Access) or LTE (Long Term Evolution) is used as a communication method, it is necessary to continuously operate a receiver circuit. Therefore, off-line calibration cannot be performed because it has to be performed during a non-operating period. Further, if background calibration, which is to be performed during an operation, is periodically performed, an unnecessary signal component having a frequency corresponding to the cycle of such calibration is generated to decrease the accuracy of a received signal.
In view of the above, an analog-to-digital conversion circuit is disclosed in U.S. Pat. No. 7,046,179. The analog-to-digital conversion circuit has a multiplexer and performs foreground calibration by switching between an input signal and a reference signal. More specifically, the analog-to-digital conversion circuit includes a calibration reference circuit and a conversion circuit. The calibration reference circuit is formed in an integrated circuit to supply a calibration reference signal. The conversion circuit is formed in an integrated circuit to include a comparison reference circuit and a comparison circuit. The comparison reference circuit supplies a plurality of reference signals. The comparison circuit supplies a plurality of comparator output signals, which correspond to the reference signals, and a comparator input signal. The comparator input signal is generated from the calibration reference signal when a calibration signal is presented. The calibration reference circuit is formed as described below. When the calibration signal is presented, the calibration reference circuit is enabled. When, on the other hand, the calibration signal is not presented, the calibration reference circuit is disabled and does not substantially consume any electrical power.
Another analog-to-digital conversion circuit is disclosed in U.S. Pat. No. 7,623,050. The analog-to-digital conversion circuit fine-tunes a reference voltage to perform foreground calibration of the offset voltage of a comparator used in the analog-to-digital conversion circuit. More specifically, the analog-to-digital conversion circuit includes an analog-to-digital converter, a multiplexer, a variable voltage source, and a calibration circuit. The analog-to-digital converter includes a first input section, a second input section, and an output section. The multiplexer is coupled to the first input section of the analog-to-digital converter. The variable voltage source is coupled to the second input section of the analog-to-digital converter. The calibration circuit controls the variable voltage source and is coupled between the variable voltage source and the output section of the analog-to-digital converter. The analog-to-digital converter compares a fixed voltage supplied through the multiplexer to a variable voltage supplied from the variable voltage source.
An analog-to-digital converter is disclosed in Japanese Unexamined Patent Publication No. 2009-159415. The analog-to-digital converter performs foreground calibration of a reception system by using a transmitter circuit. More specifically, the analog-to-digital converter is used for a receiver circuit of a communication device to perform calibration with a digital signal. The analog-to-digital converter includes an analog-to-digital conversion unit, a calibration section, a digital output generation section, and a selector switch. The analog-to-digital conversion unit converts an input analog signal to a digital signal. The calibration section is coupled to the output side of the analog-to-digital conversion unit. An output of the analog-to-digital conversion unit is input into the digital output generation section. The selector switch is provided on the input side of the analog-to-digital conversion unit. The selector switch is capable of inputting into the analog-to-digital conversion unit either an analog signal input into the receiver circuit or a calibration analog signal obtained when a calibration digital signal is subjected to digital-to-analog conversion in a digital-to-analog converter for the transmitter circuit of the communication device. The calibration section is coupled to the output of the digital output generation section, to the output of the analog-to-digital conversion unit, and to the input of the digital-to-analog converter. The calibration section is capable of acquiring a parameter for calibrating the output of the analog-to-digital conversion unit by using the calibration digital signal and a digital signal obtained when the calibration analog signal is input into the analog-to-digital conversion unit.
Another analog-to-digital converter is disclosed in Japanese Unexamined Patent Publication No. 2010-004373. The analog-to-digital converter is a serial-parallel converter that performs background calibration. More specifically, the analog-to-digital converter includes a reference voltage generation circuit, a high-order bit comparator, a plurality of amplifiers, a plurality of first selectors, a plurality of second selectors, a plurality of low-order bit comparators, a third selector, and an encoder. The reference voltage generation circuit generates a plurality of reference voltages. The high-order bit comparator divides the reference voltages into a plurality of regions, notes the divided regions, and compares the input analog voltage to a region boundary voltage to determine a region to which an input analog voltage belongs. The amplifiers output a difference voltage between the reference voltages and the input analog voltage. The first selectors select the reference voltages to be input into the amplifiers. The second selectors check the output signals of the amplifiers in the divided regions and select the output signals of the amplifiers in accordance with the region determined by the high-order bit comparator. The low-order bit comparators compare the magnitudes of two signals out of the signals selected by the second selectors to output a comparison result signal. The third selector checks the low-order bit comparators, selects the output signal of a low-order bit comparator for analog-to-digital conversion, and does not select the output signal of a low-order bit comparator for calibration. The encoder generates a digital signal in accordance with the output signal of the low-order bit comparator selected by the third selector and with the region determined by the high-order bit comparator.
A power consumption control method for a wireless receiver is disclosed in Japanese Unexamined Patent Publication No. 2010-226236. The wireless receiver is configured so that an analog-to-digital conversion section for digitizing a received signal, which is downconverted in a high-frequency section, and entering the digitized received signal into a baseband section, is capable of setting a bias current. The power consumption control method includes the following first and second steps. The first step determines, in accordance with a digital signal output from the analog-to-digital conversion section, whether a first change or a second change occurs. In the first change, the status changes from a communication signal reception state to a communication signal wait state. In the second change, the status changes from the communication signal wait state to the communication signal reception state. The second step is performed in accordance with the result of determination. More specifically, when the first change occurs, the second step sets a smaller bias current than when the second change occurs. When, on the other hand, the second change occurs, the second step sets a larger bias current than when the first change occurs.
Still another analog-to-digital converter is disclosed in Japanese Unexamined Patent Publication No. 2010-035140. The analog-to-digital converter compares converted values by using two comparators and performs calibration by updating an offset. More specifically, the analog-to-digital converter includes a reference voltage generation circuit, a first comparator, a second comparator, and a calibration circuit. The reference voltage generation circuit outputs a reference voltage. The first and second comparators compare the voltage of an input signal to the reference voltage and output a digital signal indicative of a first logic value or a second logic value. The calibration circuit compares the output of the first comparator to the output of the second comparator and outputs a first offset control signal and a second offset control signal. The first comparator sets a positive or negative offset amount for an output inversion threshold value level in accordance with the first offset control signal. The second comparator sets an offset amount for the output inversion threshold value level in accordance with the second offset control signal. The offset amount set by the second comparator has an inverse polarity with respect to the offset amount set by the first comparator.